Adding Support for Vector Instructions to 8051 Architecture

This was a group project for the Computer Architecture course at SNU under Prof. Rajeev Kumar Singh. Our team wrote a theoretical paper in which the focus is on adding support for vector instructions to the Intel 8051 architecture. The proposed architecture has a new vector register bank and a unit to decode the vector addresses. The team was composed of Akhil Alluri, Dhiraj Balakrishnan, Manvendra Singh, Rohan Verma, and Pulkit Gairola. This project can be used to demonstrate how one can add specialized vectorisation capabilities to architectures found in microcontrollers.